1. Technical Field
The invention relates to electrical testers, and, more specifically, to electrical testing of liquid crystal display (LCD) arrays.
2. Description of the Related Art
An array tester as described in U.S. Pat. No. 5,179,345 and 5,546,013 provides a means for testing the cells of an TFT/LCD display array by coupling test probes to the gate line pads and data line pads that terminate the gate lines and data lines, respectively, of the TFT/LCD array.
Importantly, when the size of the TFT/LCD display array under test is changed, the spacing of the gate lines and/or data lines and the pads terminating thereof change. In order to test such an array, the probe fixture for the gate lines and/or data lines must be redesigned to accommodate for the variation in spacing, which is a costly solution.
In addition, when the resolution of the TFT/LCD display array under test results is changed, the number of gate lines and/or data lines and pads terminating thereof changes. In order to test such an array, the probe fixture for the gate lines and/or data lines must be redesigned to accommodate for the variation in the number of gate lines and/or data lines. Moreover, the gate line drive circuitry and/or the data line drive/sense circuitry and the control routine must be updated to accommodate for the variation in the number of the gate lines and/or data lines. Such design modifications are also very costly.
Thus, there remains a need in the art for an array test system whereby the configuration of the array test system can be changed with minimal costs in order to accommodate variations in the size and/or resolution of the TFT/LCD display arrays under test.
In addition, there remains a need in the art for circuitry integrated onto the substrate that enables reconfiguration of the array test system with minimal costs.
The problems stated above and the related problems of the prior art are solved with the principles of the present invention, integrated circuits for testing a display array, which comprises an array of pixel cells formed on a substrate. Each pixel cell is coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines formed on the substrate. The gate lines and/or data lines are partitioned into a plurality of groups. For each particular group, a first probe pad and select logic is formed on said substrate. The select logic, which is coupled between the first probe pad and the lines of the particular group, selectively couples the first probe pad to the lines of said particular group based upon first control signals supplied to the select logic during a test routine whereby charge is written to, stored, and read from the array of pixel cells. In addition, a second probe pad and hold logic for each particular group may be formed on the substrate. The hold logic, which is coupled between the second probe pad and the lines of the particular group, selectively couples the second probe pad to the lines of the particular group based upon second control signals supplied to the hold logic during the test routine. The apparatus provides a flexible interface between the array under test and the test system, which minimizes the redesign costs when the size and/or resolution of the array under test is varied.